Controllable delay circuits are needed in a wide variety of technical application sectors in order to delay an input signal in defined fashion as a function of a control value. One application example is a confocal microscope, in which pulsed laser light is emitted by means of a laser light source in order to illuminate the specimen to be investigated. The detected light proceeding from the specimen is detected by means of a detection device. The intensity of the laser light beam generated by the laser light source is controlled by a first control signal. A second control signal is provided in order to control the detection device. Because the laser light beam generated by the laser light source produces the detected light beam, for example by reflection of the laser light beam at the specimen to be illuminated, or by bringing about fluorescence effects, the detected light is to be expected at the detection device within a defined delay time after emission of a laser light beam. The second control signal is therefore often a time delay of the first control signal. Generation of the second control signal from the first control signal requires very precise circuits, adjustable with high resolution, for controllably delaying an input signal. The delay times are usually on the order of 1 to 2 nanoseconds.
One such circuit for delaying an input signal in a microscope is disclosed in DE 10 2009 055 993 A1. Here firstly a coarse delay is generated by means of a first delay unit, and then a fine delay is generated by means of a second delay unit. The second delay unit is made up of a pulse shaper that outputs signals to two shift registers. The signals outputted by the two shift registers are combined by means of a double data rate (DDR) flip-flop in order to generate and output the output signal.
The circuit known from the existing art is disadvantageous in that the circuit is of relatively complex construction, and in that the resolution with which the delay times can be adjusted is comparatively low. Although the resolution of the circuit can be increased within certain limits by increasing the clock rate of the shift register of the second delay unit, the complexity of the circuit prevents the clock rate from being increased arbitrarily.